1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device and a method for fabricating the same that reduces a short channel effect.
2. Background of the Related Art
Generally, in fabricating a semiconductor integrated circuit, various efforts continue at reducing the dimensions of a metal oxide semiconductor field effect transistor (MOSFET) constituting a semiconductor chip integrated circuit that has excellent perfomance and high packing density. As a result of such efforts, a semiconductor integrated circuit and a method of making the same have been scaled down to a sub-micron size.
In reducing the dimensions of the semiconductor device, the vertical dimension as well as the horizontal dimension should be reduced to balance the characteristics of various devices. In other words for a transistor, if the distance between a source and a drain becomes close, a characteristic of the device is varied, which causes an undesired characteristic such as the short channel effect. To improve such short channel effects caused by high packing density, a lightly doped drain (LDD) structure is adopted in which a low density junction is formed below a gate sidewall.
A related art semiconductor device and a method for fabricating the same will now be described. FIG. 1 is a diagram showing a sectional view of the related art semiconductor device.
As shown in FIG. 1, a gate insulating film 12 is formed on a semiconductor substrate 11. A gate electrode 13a is formed in a predetermined region on the gate insulating film 12. A sidewall insulating film 16 is formed at both sides of the gate electrode 13a. A heavily doped impurity region 17 having an LDD structure is formed in a surface of the semiconductor substrate 11 at both sides of the gate electrode 13a.
FIGS. 2a to 2d are diagrams showing sectional views of a method for fabricating the related art semiconductor device. As shown in FIG. 2a, a channel ion is implanted into the entire surface of the semiconductor substrate 11. A gate insulating film 12 is formed on the semiconductor substrate 11 into which the channel ion is implanted. A polysilicon layer 13 for a gate electrode is formed on the gate insulating film 12. Subsequently, a photoresist 14 is deposited on the polysilicon layer 13 and then patterned by exposure and developing processes to define a gate region.
As shown in FIG. 2b, the polysilicon layer 13 is selectively removed using the patterned photoresist 14 as a mask to form a gate electrode 13a. As shown in FIG. 2c, the photoresist 14 is removed, and an n type lightly doped impurity ion is implanted into the entire surface of the semiconductor substrate 11 using the gate electrode 13a as a mask to form a lightly doped impurity region 15 in the surface of the semiconductor substrate 11. Thus, the lightly doped impurity region 15 is formed at both sides of the gate electrode 13a.
As shown in FIG. 2d, an insulating film (not shown) is formed on the entire surface of the semiconductor substrate 11 including the gate electrode 13a. The insulating film is then etched back to form a sidewall insulating film 16 at both sides of the gate electrode 13a. Subsequently, an n type heavily doped impurity ion, which is used for a source and a drain, is implanted into the entire surface of the semiconductor substrate 11 using the sidewall insulating film 16 and the gate electrode 13a as masks. A heavily doped impurity region 17, which is connected with the lightly doped impurity region 15, is thereby formed in the surface of the semiconductor substrate 11 at both sides of the gate electrode 13a.
However, the related art semiconductor device and method for fabricating the same have various problems. In the related art semiconductor device and the method for fabricating the same reliability deteriorates because of a short channel effect caused by diffusing impurity ions of the heavily doped impurity region into the channel region.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.